NVIDIA said on July 26, 2026 that it is deploying its Vera CPU across electronic design automation (EDA) workflows to accelerate the design of next-generation CPUs and GPUs. Two production applications were evaluated: Cadence's Jasper formal verification platform and Synopsys' VCS functional verification solution. NVIDIA states that both applications showed up to 1.5x higher performance on selected workloads. Vera is built from 88 custom NVIDIA Olympus CPU cores, an LPDDR5X memory subsystem, and second-generation NVIDIA Scalable Coherent Fabric. ASAP summarizes this from NVIDIA's official blog post by Ivan Goldwasser.

The workload on display is verification, not training

The workloads NVIDIA chose to highlight are not AI training or inference but the verification stage of chip design. The post explains that logic simulation, formal verification, and portions of digital implementation often depend on fast individual cores, efficient memory systems, and strong overall throughput. The order in which those three conditions appear describes the character of the work. Verification behaves nothing like large parallel matrix math; its performance is bound to how fast a single thread turns and how consistent memory access remains. NVIDIA says Vera suits environments that mix latency-sensitive jobs with large-scale regression testing. An accelerator company introducing its CPU picked a domain where GPUs are not the answer, and that choice by itself indicates where the bottleneck in an EDA pipeline sits.

The post never says what 1.5x is measured against

The sentence to read most carefully is the one containing "up to 1.5x." NVIDIA states only that Cadence Jasper and Synopsys VCS showed up to 1.5x higher performance on selected production-class workflows, and it does not disclose the comparison baseline. Which CPU it was measured against, at what configuration and core count, and what share of a full regression the selected workloads represent are all absent. The qualifier "up to" should be read literally as well: up to 1.5x is not an average of 1.5x, but the ceiling of the most favorable case. What remains solid here is not the multiplier but something else. Commercial verification tools from Cadence and Synopsys ran production-class workflows on NVIDIA's own cores, and both EDA vendors were part of publishing the result. In the EDA industry, porting and certifying tools is a process that moves far more slowly than benchmark numbers, and reaching the stage where early results are announced jointly is the more substantive signal.

What 88 cores plus LPDDR5X is aimed at

Vera's configuration lines up item by item with what verification workloads demand. The 88 custom Olympus cores answer the pattern of dispatching large numbers of independent jobs in parallel, as regression testing does, and the second-generation Scalable Coherent Fabric exists to keep latency consistent as core counts rise. The notable choice is the LPDDR5X memory subsystem. Selecting a power-efficient memory family over what server CPUs typically carry suggests the design target is the balance of per-core performance against throughput per watt rather than maximum absolute bandwidth. Verification farms run thousands of jobs continuously over multi-day cycles, so power is a large share of total cost of ownership, and under those conditions how many jobs a rack sustains matters more to the real design cycle than peak performance. NVIDIA published no power figures in this announcement, so this reading is inferred from the configuration rather than confirmed by measurement.

The loop of building your own chips with your own chips

The structural implication of this announcement is not the multiplier but the loop: NVIDIA has put its own CPU into its own chip design process. The post does not stop there and previews the next step, saying NVIDIA will build on Vera with the next-generation Rosa CPU powered by the NVIDIA Rigel core while continuing optimization across its CPU roadmap. This arrangement cuts two ways. One is an internal feedback loop, where design teams fold real usage data from their own CPU into the next generation, and a demanding workload like EDA doubles as a permanent validation environment. The other is a sales argument, since "we run our most valuable design asset on it" is evidence aimed at external customers. At the same time the structure concentrates dependency inside one company. When design tools, execution hardware, and the final product share a roadmap, bottlenecks get addressed faster, but the routes around a roadmap that slips get narrower too.

Why swapping EDA infrastructure takes more than a benchmark

Replacing hardware in an EDA environment is not decided by performance comparisons. Reproducibility of verification results is central to certification, so identical tests must produce identical outcomes; commercial tool licenses are tied to core counts and execution environments, so a change in hardware configuration shifts the cost structure with it; and years of accumulated regression scripts and in-house tooling are frequently written against a specific environment. That this announcement uses the phrase "early results" and names only two applications most plausibly reflects the length of that process. So the thing to watch next is not a bigger multiplier but a longer list. Whether coverage expands beyond formal verification and functional simulation into synthesis, place and route, timing analysis, and physical verification, and whether comparable results get reported from production flows at semiconductor companies outside NVIDIA, are the criteria that matter.

What semiconductor teams should take from this

The practical takeaway for semiconductor organizations is redefining how verification infrastructure gets evaluated. Both fabless and memory design teams operate in a structure where verification farm throughput directly governs tapeout schedules, and investment decisions in this area have often been made as extensions of an existing server configuration. Three checks follow. First, is the real bottleneck in your regression measured and decomposed job by job into insufficient core count, single-core speed, or memory latency? The three conditions NVIDIA listed show that without that decomposition no hardware choice can be justified. Second, have you confirmed the contract terms for how your EDA tool licenses are tied to core counts and execution environments? Third, do you have a rule requiring that when a vendor's "up to N times" figure is carried into an internal review document, the presence or absence of a disclosed baseline is noted? This case demonstrates that a multiplier without a stated comparison shows up even in primary sources.

What is established and what is missing

Four things are established. NVIDIA has deployed the Vera CPU into its EDA workflows; Cadence Jasper and Synopsys VCS showed up to 1.5x higher performance on selected workloads; Vera consists of 88 custom Olympus cores, an LPDDR5X memory subsystem, and second-generation Scalable Coherent Fabric; and a Rigel-based Rosa CPU is previewed as the next generation. The comparison baseline, the measurement configuration, power figures, and the share of the workload covered are not disclosed. The narrative of a chip vendor building its next chip on its own silicon is a strong one, but the place it gets tested is the next report coming out of a production flow at a semiconductor company other than NVIDIA.

Source: NVIDIA official blog announcement on using the Vera CPU for EDA (July 26, 2026, by Ivan Goldwasser), specifying up to 1.5x higher performance on selected workloads for Cadence Jasper and Synopsys VCS, 88 custom Olympus CPU cores, the LPDDR5X memory subsystem, second-generation Scalable Coherent Fabric, and plans for the next-generation Rigel-based Rosa CPU. Summarized by ASAP.