IBM Unveils a 0.7nm 'Nanostack' Transistor, Claiming 50% More Performance Than 2nm

IBM says it has built the world's first sub-1nm transistor technology at the 0.7nm (7-angstrom) node, The Next Web reported on June 25, 2026. The technology, called nanostack, is a three-dimensional nanosheet transistor architecture that packs roughly 100 billion transistors onto a fingernail-sized chip, according to IBM. The company says density roughly doubles, performance improves by up to 50%, and energy efficiency improves by up to 70% versus its 2021 2nm chip. This article organizes the facts on the basis of The Next Web's report and IBM's stated figures.

What Was Shown at VLSI 2026

IBM presented the nanostack transistor, corresponding to a 0.7nm (7-angstrom) node, as a research milestone at VLSI 2026. The company describes it as the industry's first three-dimensional, nanosheet-based transistor architecture, extending logic scaling into angstrom-scale territory. Jay Gambetta, director of IBM Research, said, "With our new nanostack architecture, we're not just making smaller transistors, we're reinventing how chips are built." The heart of the announcement is not that individual devices got smaller, but that the axis along which devices are arranged has changed.

How Not to Misread the '0.7nm' Label

The 0.7nm figure is a generation label rather than a physical dimension. No specific part of the transistor literally measures 0.7 nanometers; the name follows an industry convention for the node that comes after 2nm. Miss that convention and it is easy to picture a device only a few atoms wide. IBM says it raised density at this generation by stacking nanosheets vertically into a three-dimensional structure. In other words, the number shrank not because line widths were cut that much, but because it is the name assigned to the generation that fits more devices into the same area.

Why Stacking Vertically Matters

The point worth noticing here is that the direction of scaling has changed. Chipmakers have long raised density by shrinking line widths on a flat plane, but as those widths approach atomic scale, flat scaling is hitting a physical wall. Nanostack's choice to stack nanosheets upward into a three-dimensional structure reads as an attempt to route around that wall. Just as a city with no land left builds upward, a chip that has saturated its plane climbs into layers. The roughly doubled density owes more to this structural shift than to any further trimming of line widths.

The Numbers Behind the Gains

Nanostack integrates roughly 100 billion transistors onto a single fingernail-sized chip, IBM says. The company adds that density roughly doubled compared with the 2nm chip it announced in 2021. Performance rises by up to 50% and energy efficiency improves by up to 70%, while SRAM, the on-chip memory, scales by 40%, the company says. Key equipment makers Lam Research, Tokyo Electron, SCREEN, and ASML took part in developing the process. The qualifier "up to" is worth not skimming past. The 50% and 70% are ceilings, and under different conditions the real gain may fall below them.

What It Signals for Korea's Chip Industry

The announcement also sends an indirect signal to Korea's industry. In the advanced-logic and back-end contest between Samsung Electronics and SK hynix, three-dimensional stacking is already a central theme, and IBM's research result can be read as evidence that the direction is sound. That said, IBM is the research and design party while actual mass production falls to the foundry ecosystem, so this milestone does not translate directly into any one company's advantage. If anything, the fact that equipment makers such as Lam Research, Tokyo Electron, and ASML joined the development shows that the next-generation race is a matter not only of device design but of the entire equipment and materials supply chain.

How Far Should You Trust These Numbers

IBM's figures are a research-stage result, and a path to mass production is estimated at five years out at the earliest. The stated performance and efficiency gains rest on IBM's own materials, and independent production validation has not yet occurred. Whether a lab demonstration translates into manufacturing yield and cost will depend on the equipment ecosystem and process maturation. History offers plenty of cases where conference-stage scaling claims slipped years behind their production timelines. So for now these numbers are best read as a ceiling of what is possible, with verification held over as something to confirm again on a production line.

Sources: The Next Web