NVIDIA Moved the Memory Controller Into the HBM Stack: NVHBM Claims 30% More Bandwidth, 15% Less Power, and 25% More Compute-Die Area

NVIDIA expanded its NVLink Fusion platform on August 26, 2026 with NVHBM, a custom high-bandwidth memory technology. NVHBM relocates the memory controller that traditionally sits on the XPU compute die into the HBM base die, and NVIDIA states that compared with standard HBM4E it delivers up to 30% greater memory bandwidth, 15% lower HBM power consumption, and frees up to 25% more area on the XPU compute die. The first collaborator is Amazon's Annapurna Labs, which will support NVLink Fusion starting with its next-generation Trainium4 chip. ASAP works only from figures verifiable in NVIDIA's own announcement to show that this is less a memory specification upgrade than a design for pulling the custom-silicon camp inside NVIDIA's own standards.

Relocating one component produced three different kinds of gain at once

The problem NVIDIA points to is placement. The announcement states that "traditional HBM architectures place the memory controller on the XPU die, consuming valuable silicon area that could otherwise be dedicated to compute." NVHBM moves that controller into the memory stack instead. According to the announcement, NVHBM is "built on the same technology that NVIDIA will use for future GPUs" and "integrates NVIDIA's custom memory controller into the HBM base die."

The relocation produces three effects. Against standard HBM4E, memory bandwidth rises by up to 30%, HBM power consumption falls by 15%, and up to 25% more area is freed on the XPU compute die.

What matters is that these are three different species of gain. The 30% is a performance figure, the 15% is an operating-cost figure, and the 25% is headroom available to whoever designs the next chip. In silicon design these three usually trade against one another: raise bandwidth and power rises, save area and performance suffers. A claim that all three moved the same direction from changing where one component physically sits reads less like a faster circuit than like a redrawn system boundary.

Why the 25% area figure outlasts the performance numbers

Of the three figures, the one with the longest practical reach is probably not the 30% bandwidth but the 25% of freed compute-die area. Bandwidth and power are felt immediately in this generation; recovered area carries forward as design latitude for the next one.

Once the space the memory controller occupied is vacant, a chip designer can spend it on more compute units, on a larger on-chip cache, or on shrinking the die itself to improve yield and unit count per wafer. Each choice pays differently. More compute units raise throughput at the same power; a smaller die delivers the same performance for less money. On a leading-edge process, die area is effectively price, so 25% of it is simultaneously a performance opportunity and a cost opportunity.

The announcement, however, stops at the claim that area is freed. It does not say how much additional performance results from filling that area with any particular thing. The 30% and 15% read as measured results, while the 25% remains potential. Anyone quoting this announcement is more accurate placing the three figures on different tiers rather than the same one.

The real subject is not memory but the NVLink Fusion gateway

NVHBM is not a standalone product announcement but one component of an expansion to NVLink Fusion, which is the platform this news is actually about. NVLink Fusion is a rack-scale platform that lets partners connect custom XPUs and CPUs on a common architecture to build semi-custom AI infrastructure. Participants get access to "NVIDIA NVLink chiplets, NVLink-C2C, NVLink Switches and NVIDIA MGX systems," alongside what NVIDIA describes as "a broad ecosystem of CPU partners, ASIC designers, system manufacturers and technology providers."

Seen in that frame, NVHBM's role changes. The companies joining NVLink Fusion are the ones that decided not to buy NVIDIA GPUs: cloud providers and ASIC houses designing their own accelerators. From NVIDIA's position these are lost customers, and NVLink Fusion places the chips they built onto NVIDIA's interconnect and rack standards. The compute die belongs to someone else, but the wiring, the switches, and the system around it are NVIDIA's.

NVHBM adds one more layer to that. When a partner designing its own silicon adopts HBM carrying NVIDIA's custom memory controller, that chip's memory subsystem design follows NVIDIA's specification too. The 30%, 15%, and 25% are genuine gains for the partner and, at the same time, reasons not to switch standards later. NVIDIA's description of NVHBM as built on the same technology it will use for future GPUs summarizes the arrangement precisely: NVIDIA's own GPUs and someone else's XPUs run on one shared memory technology.

What it means that Amazon is the first partner

Amazon's Annapurna Labs, named as the first collaborator, is the group that has designed the Trainium accelerator line. According to the announcement, Annapurna will support NVLink Fusion with its next-generation Trainium chips starting with Trainium4. Nafea Bshara, Vice President of Annapurna Labs at Amazon, said that "NVHBM represents a new architectural approach to advancing high-bandwidth memory performance and efficiency."

The pairing is notable because the camp that pushed hardest and longest on in-house silicon is the one adopting NVIDIA's standard first. Trainium existed to reduce dependence on NVIDIA, and its successor will now stand on NVIDIA's interconnect and memory technology. Designing your own chip and excluding NVIDIA have stopped being the same statement.

How to read that shift depends on where you stand. One reading is a pragmatic division of labor: the custom-silicon camp buys the hard layers, interconnect and memory, rather than building them, and concentrates on compute-core design. The other reading is that a project launched to escape NVIDIA has settled inside NVIDIA's ecosystem. Either way, one fact holds. At the rack, wiring, and memory layers, NVIDIA's position persists independently of GPU market share.

The conditions left unverified

NVIDIA's NVHBM announcement leaves four conditions unsettled: the manufacturer, the schedule, the measurement setup, and the size of the partner list. First, no memory manufacturer is named. NVIDIA says only that it is "establishing a standard NVHBM implementation, available from multiple memory providers," and the announcement does not identify who actually builds it. Given the structure of HBM supply, that item governs both schedule and volume.

Second, there is no date. Trainium4 support is described as beginning with next-generation Annapurna chips, but no shipping window or validation milestone is given. In semiconductor announcements, a specification without a date is safest read as a roadmap item.

Third, the measurement conditions behind 30%, 15%, and 25% are absent. The comparison target is stated as standard HBM4E, but the workload, the stack configuration, and the number of runs are not. The figures also mix bounded and unbounded phrasing, so the bandwidth and area numbers are more accurately quoted as ceilings while the 15% power figure is stated more flatly.

Fourth, no participant beyond Annapurna is disclosed. NVIDIA references a broad ecosystem, yet Amazon is the only collaborator named in this announcement. Whether NVLink Fusion becomes the common gateway for the custom-silicon camp or remains a single partnership will be decided by how many more names appear in the next one.

Source: NVIDIA's official blog announcement of NVLink Fusion and NVHBM (August 26, 2026), compiled by ASAP